This invention is in the field of nonvolatile memory devices, and specifically relates to Electrically Erasable and Programmable Read-Only (EEPROM) devices.
EEPROM devices in general, and methods for making such devices, are well known in the art. Typically, an EEPROM memory cell structure has a source region, a drain region, a floating gate, a control gate, and a dielectric layer isolating the control gate from the floating gate.
The source and drain regions are typically disposed as lateral doped areas as shown in U.S. Pat. No. 4,698,787, U.S. Pat. No. 4,796,228 and U.S. Pat. No. 4,849,369. Such configurations take up a significant amount of horizontal space in the memory cell structure because the surface source and drain areas are defined by conventional photolithography.
The source and drain regions have also been disposed as vertical doped areas in a trench structure which also contains gate regions as shown in U.S. Pat. No. 4,979,004. Such devices include pleated gates that are less reliable than the typical stacked poly gate or mesa structure. Defects of the semiconductor material concentrate in the bottom of the trench, where the pleated gate structure is located, thus making the pleated gate devices vulnerable to such defects.
Another disadvantage to the prior art is that individual electrical contacts must be connected to each gate, source and drain region. This requires quite an extensive amount of conductive interconnections and space. Such contacts to the drain, for example, have been made by a silicide film pad and selective tungsten plugs as described in an article by Y.S. Hisamune, et al., A 3.6um.sup.2 Memory Cell Structure for 16MB EPROMS, IEDM 89-583. Such technology requires multilayers of metallization in order to achieve operability of such contacts including at least one layer of metallization for word lines and at least one additional layer for bit lines. Thus, for a high density memory the current state of art requires complicated production and manufacturing processes. Such complicated processes are expensive.
Therefore, there has been a long standing need for a high density, reliable EEPROM structure with a reduced memory cell area that is contactless with only a single layer of metallization.